1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly the invention relates to the formation of gate electrodes for metal-oxide-semiconductor field effect transistors (MOSFETs).
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs).
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, theses devices are referred to simply as FETs, and are so referred to in this disclosure.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate insulator thickness are also typically reduced in order to produce a FET with the desired electrical characteristics.
As is well-known, the gate electrode of a FET is commonly formed from a patterned layer of polycrystalline silicon. Polycrystalline silicon is also referred to polysilicon. The polysilicon gate electrodes are commonly doped such that the gate electrodes of n-channel FETs (NFETs) are n-type, and the gate electrodes of p-channel FETs (PFETs) are p-type. The doping of the polysilicon gate electrode affects its work function. The work function in turn affects the threshold voltage of the FET.
Since doped polysilicon is a semiconductive material, it tends to experience the formation of a depletion region adjacent to the interface between the gate electrode and the gate insulator when a voltage is applied to the gate electrode. As device scaling has substantially reduced the thickness of the gate insulator layer, the width of the depletion region in the doped polysilicon gate electrode has come to play a more significant role in determining the electrical characteristics of the FET. Unfortunately, the occurrence of this depletion region in the gate electrode tends to degrade transistor performance.
What is needed is a gate electrode that provides approximately the same work function values as doped polysilicon while substantially avoiding the effects of depletion region formation.